AREA EFFICIENT, LOW QUIESCENT CURRENT AND LOW DROPOUT VOLTAGE REGULATOR USING 180nm CMOS TECHNOLOGY

This paper illustrates the design and implementation of a Low Drop out voltage regulator which consumes low power and occupies less area. The regulator uses single stage error amplifier hence area consuming compensation capacitor is avoided. It needs only 16 µA quiescent current making it suitable for low power applications. The proposed regulator has been designed in 180 nm CMOS technology and performance is tested using spice tool and layout is done using MAGIC VLSI tool. Simulation results show that the LDO has a line regulation of 0.001V/V and load regulation of 0.002V/mA. The LDO occupies an area of 70µm ? 80µm and power dissipation is 20µW.