PERFORMANCE IMPROVEMENT OF REVERSIBLE LOGIC ADDER

Reversible logic is gaining importance in the context of upcoming fields such as nanotechnology, cellular automata, quantum level computation and low power VLSI design. The most attractive feature in reversible circuits is that there is one to one correspondence between input and output vectors. Therefore these circuits do not lose any information during computation. In this work we have improved the performance of reversible logic adder by modifying its structure. A delay and power efficient vedic multiplier has been implemented using proposed adder. All the circuits have been designed at 90 nm CMOS technology using Cadence Virtuoso software. Based on the results, it is concluded that the performance of a carry look ahead (CLA) adder gives best performance by changing the type of reversible gate used in its structure. The performance improvement is in terms of reduced number of gates by almost 60% reduced ancillary inputs by 46% and reduced number of garbage outputs by almost 48%. The proposed CLA adder may also find many applications in multiply and accumulate units.